For semiconductor integrated circuit devices, miniaturization and higher-integration of Metal Oxide Semiconductor (MOS) transistor have been achieved. With the miniaturization of the transistor, a width of a wiring coupled to the transistor tends to be reduced. Operation speed of a semiconductor integrated circuit is limited by a resistance of a wiring and parasitic capacitance. In order to reduce a resistance of a narrow wiring, copper or copper alloy has been used instead of aluminum.
Improving patterning accuracy of a copper wiring is difficult. Therefore, a damascene method is employed that forms a trench in an inter-layer insulating film in which to bury a copper wiring. Copper has a property that degrades insulating characteristics of an insulating film when the copper is diffused in the insulating film. In order to prevent diffusion of copper, a barrier metal layer is formed over the surface of the trench, a copper wiring is buried in the concave part, unnecessary metal layers over the inter-layer insulating film are removed by chemical mechanical polishing (CMP) etc., and an insulating cap layer for preventing diffusion of copper such as SiN, SiCN, or SiC is formed.
With the advancement of higher-integration, problems such as voids are caused in a damascene copper wiring, and measures to tackle the problems have been studied.
Japanese Laid-open Patent Publication No. 2001-15508 points out that when an aspect ratio of a trench becomes large, the trench may not be filled with conductive material completely and this causes a cavity called a void, a phenomenon generally referred to as the step coverage problem. Japanese Laid-open Patent Publication No. 2001-15508 proposes controlling the increase in the aspect ratio by making a distance between side walls larger as the trench depth becomes greater.
Japanese Laid-open Patent Publication No. 2006-203019 points out that with miniaturization of a wiring, in the upper parts of the sides of a via and a trench, a barrier metal film becomes thicker whereas the barrier metal film becomes thinner in the lower parts of sides of the via and the trench, again due to the step coverage problem. Thus, a seed layer is not sufficiently deposited and that makes burying a Cu film by electrolytic plating difficult, and a buried failure such as a void is generated in a via. Thus, Japanese Laid-open Patent Publication No. 2006-203019 proposes to round a corner of a bottom of a trench.
Japanese Laid-open Patent Publication No. 2006-287086 points out that a wiring or a via plug can be damaged due to electric field concentration or physical stress. Japanese Laid-open Patent Publication No. 2006-287086 proposes making a barrier metal film covering the side surface of the via hole thicker than that of covering the bottom surface.
With the advancement of higher-integration, multi-layered wirings have been advanced as well. For example, multi-layered wirings that exceed ten layers have been used. A lower wiring near a transistor is narrow and thin, while an upper layer wiring is wide and thick. As integration advances, more power is required to be input to a chip. A power-supply wiring with lower resistance is desired and a thickness of the upper wiring tends to be increased.
There is a configuration to reduce power consumption of a small-sized portable device, etc., in which a DC-DC converter is provided to reduce a voltage when output from a power amplifier is low. In this application, an inductor that may flow, for example, a current of 100 mA order. Other applications may require an inductor that can flow a large current.
In order to obtain a wiring that enables to flow a large current, forming a thick wiring such as several microns thick may be desired. However, using such thick wirings which have not been used before causes new problems.